This invention relates to reference voltage generators and more specifically to reference voltage generators for use in MOS memories such as read only memories (ROMs), erasable programmable read only memories (EPROMs) and other MOS devices.
As is known in the art, a ROM is a device which stores information such that the information stored cannot be changed. Typical ROMs include a plurality of locations or addresses where information is stored and a plurality of address lines for selecting a location from which to retrieve the stored information. A partial schematic diagram of such a ROM illustrated in FIG. 1.
Referring to FIG. 1, a ROM constructed in accordance with the prior art includes an N channel or "NMOS" transistor 10 coupled between a bit line 12 and ground. (The letters next to the transistors in the drawings indicate whether they are P channel ("PMOS") or N channel ("NMOS") transistors.) NMOS transistor 10 includes a gate lead 14 coupled to a word line 16. During fabrication, NMOS transistor 10 is either rendered operative or inoperative (e.g. by doping the channel to raise the threshold voltage above 5 volts) depending upon whether it is desired to use transistor 10 to store a binary 1 or a binary 0. If rendered operative, during a read operation, the voltage on word line 16 is high (typically 5 volts) causing transistor 10 to turn on. However, if transistor 10 is inoperative, when the voltage on word line 16 is raised, transistor 10 does not turn on. The state of transistor 10 is sensed by a sense amplifier 28 which provides an output signal indicative of the state of transistor 10 as described below.
Bit line 12 is connected to VCC (typically 5 volts) via an NMOS transistor 18 and a resistor 20. Bit line 12 is also coupled to a reference voltage generator 22 via a reference voltage lead 23 and an NMOS transistor 24. The gate of NMOS transistor 24 is connected to VCC, and transistor 24 acts as a resistor. During operation, bit line 12 is charged to the reference voltage V.sub.REF present on lead 23. When it is desired to read the bit of data stored in transistor 10 (corresponding to whether transistor 10 is operative or inoperative), the voltage on word line 16 is raised to approximately 5 volts and the voltage on the gate lead of NMOS transistor 18 is raised to approximately 5 volts turning transistor 18 on. When that happens, if transistor 10 is inoperative, a voltage higher than the reference voltage V.sub.REF will be present at node 26. This voltage is presented to sense amplifier 28 which provides an output signal on an output lead 30 indicative of the fact that NMOS transistor 10 did not turn on. However, if NMOS transistor 10 is operative, raising the voltage at word line 16 causes NMOS transistor 10 to act as a closed switch, causing the voltage on bit line 12 to be pulled to ground. Since the gate of transistor 18 is at a high voltage, node 26 is also pulled to ground, and sense amplifier 28 provides an output voltage on lead 30 indicating that NMOS transistor 10 turned on.
It should be noted that it is not necessary to use a reference voltage generator such as reference voltage generator 22, but it is often desirable because of the resulting reduction in the time needed to retrieve data from the ROM. Without reference voltage generator 22 to bias bit line 12, after raising the voltage at the gate of transistor 18, if transistor 10 were non-operational, one would have to wait until bit line 12 was charged via transistor 18 before being able to sense the state of transistor 10. Thus, by biasing bit line 12, the propagation delay between the time transistor 18 turns on and the time the voltage at the input lead of sense amplifier 28 reliable indicates the state of transistor 10 is reduced.
In the ROM of FIG. 1, the gate of transistor 18 is connected to a Y decode line 32. Y decode line 32 and word line 16 are activated by having signals placed thereon in response to address signals received by the ROM. In this way the address signals can select an individual MOS transistor such as NMOS transistor 10 as the source of data to be transmitted on lead 30. As can be seen in FIG. 1, reference voltage lead 23 is also coupled to a plurality of other bit lines (shown as three other bit lines 38, 40 and 42) via a plurality of NMOS transistors (shown as transistors 44, 46, and 48), respectively. Boxes 50, 52, and 54 coupled to bit lines 38, 40 and 42 contain circuitry identical to that in box 56. Thus reference voltage generator 22 biases a plurality of bit lines. In some prior art ROMs, reference voltage generator 22 biases 256 bit lines. Because of this the output impedance of reference voltage generator 22 must be low enough so that if some of the bit lines are pulled low, reference voltage generator 22 can provide enough current so that the remaining bit lines will remain at reference voltage V.sub.REF. Because of this requirement, prior art reference voltage generator 22 consumes a large amount of power even if the ROM shown is not selected, since it continues to bias the bit lines regardless of whether the ROM is selected. (As is known in the art, typical systems include a plurality of ROMs and other devices connected to a common data bus. ROMs typically include a select pin for receiving a select signal provided by a host CPU to select that ROM as a souce of data.)